Physical Design Flow using cadence

Cadence is an Electronic Design Automation (EDA) environment in which different applications and tools can are integrated together. This allows all the stages of IC design and verification to be done in a single environment. The different tools are supported by different fabrication technologies allowing for customization of the Cadence environment to fit the particular technology.


➢ Cadence Design Flow – Overview

➢ Overview of features supported by new tools

  • Code a design in Verilog to the design specification that is provided.

  • Compile, elaborate and simulate your design.

  • Synthesize your design.

  • Design for Test.

➢ Functional Verification flow using Incisive

  • Code (block, expression, toggle, state, and arc) coverage

  • Data-oriented functional coverage using SystemVerilog cover groups

  • Control-oriented functional coverage using SystemVerilog assertions and the PSL

➢ RTL Synthesis & DFT flow using Genus

  • Navigate the design database and manipulate design objects

  • Constrain designs for global synthesis and run static timing analysis

  • Optimize RTL designs for timing and area using several strategies

  • Diagnose and analyze synthesis results



➢PD flow with Innovus that includes

  • Floor Planning

  • Power Planning

  • Placement

  • CTS

  • Routing

  • Generation of GDSII

➢ STA with Tempus

  • Identify and apply timing debug techniques using the Global Timing Debug interface

  • Analyze a design for timing combined with signal integrity (SI)

  • Run parallel processing techniques like distributed MMMC and Distributed Static Timing Analysis (DSTA)

Basic knowledge of Verilog is desired but optional.

Date: 16th March  2019

An email enclosing the payment link will be sent to the participant's registered email address after registration. A registration fee of INR 700 per Individual is to be paid towards Pragyan, NIT Trichy to complete the registration process for the workshop.

Organiser: Cadence supported by Entuple Technologies

Number of participants per team: 1

Duration: 6 Hours

Participants should bring their own laptop for this workshop.

Navneeth N : +91 9003886645

Ganesha VS : +91 9487565740

Email Id :  or

1) Does the workshop have any prerequisites?

There are no prerequisites for the workshop. Any student with an interest can attend the workshop.


2) How should the payment be made for the workshop?

Payment can be made online. Payment guidelines will be mailed to the participant’s mail-id once registered.


3) On what basis are workshop registrations confirmed?

Registrations are confirmed after payment on first come first serve basis. Confirmation of your participation is subject to availability.


4) Will the fees paid for the workshop be refunded in case I fail to attend the workshop?

Fees once paid, is strictly non-refundable. Requests for refund will not be encouraged.


5) Will accommodation be provided?

Yes. We provide accommodation depending on the availability and your place of residence. You will have to register separately for that. Stay tuned to the website for updates on accommodation.


6) Will certificates be provided?

Yes. A certificate from Pragyan, the student-run ISO 9001:2015 & ISO 20121:2012 certified techno-managerial organisation of NIT Trichy will be provided after the completion of the workshop.

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